HC27 (2015)

Flint Center, Cupertino, CA, Sunday-Tuesday, August 23-25, 2015.

Full Program Zipfile (130MB)

[accordion] [tabs] [tab title=”At A Glance”]
  • Sunday 8/23: Tutorials
    • 8:00 AM – 9:00 AM: Breakfast
    • 9:00 AM – 12:15 PM: Deep Learning
    • 12:15 PM – 1:30 PM: Lunch
    • 1:30 PM – 5:35 PM: Makers from Hobbyists to Professionals
    • 5:45 PM – 7:00 PM: Wine and Cheese Reception
  • Monday 8/24: Conference Day 1
    • 8:15 AM – 9:15 PM: Breakfast
    • 9:15 AM – 11:00 AM: IoT
    • 11:30 AM – 12:30 PM: Keynote 1:
    • 12:30 PM – 1:45 PM: Lunch
    • 1:45 PM – 3:45 PM: Multimedia and Signal Processing
    • 4:15 PM – 6:15 PM: HPC and Cloud
    • 6:15 PM – 7:15 PM: Reception
  • Tuesday 8/25: Conference Day 2
    • 7:30 AM – 8:30 AM: Breakfast
    • 8:30 AM – 10:00 AM: FPGAs
    • 10:30 AM – 12:00 PM: GPUs
    • 12:00 PM – 1:15 PM: Lunch
    • 1:15 PM – 2:15 PM: Keynote 2: 5G
    • 2:45 PM – 4:15 PM: Applications
    • 4:45 PM – 6:45 PM: Processors
    • 6:45 PM – 7:00 PM: Closing Remarks
[/tab] [tab title=”Tutorials”]

Tutorials

Sun 8/23 Tutorial Title Presenter Affiliation
8:00 AM Breakfast
9:00 AM Deep Learning Architectures, algorithms and applications Roland Memisevic University of Montreal
[spoiler title=”Abstract:“]Deep Learning is the current, and third, wave of wide-spread scientific interest in neural networks in the last 60 years. It is based on the insight that complex data processing tasks, like recognizing objects in images, translating text between languages, or controlling robots, can be best addressed with systems that are (i) adaptive, and (ii) serial in the sense that they use multiple stages of non-linear processing.The first, adaptivity, makes it possible to train rather than program the system with example data. This is the core idea behind machine learning, and it allows us to solve tasks that would be too hard to solve by hand. The second, deep, multi-layered processing, refers to the idea of composing highly nonlinear, complex systems from relatively simple, serially executed building blocks. This makes it possible to re-use computations and exploit invariances, that abound in most natural data.In all common Deep Learning models, the computational building blocks are simple, naturally parallel computations (such as matrix multiplications). This gives neural networks the benefit of being able to very easily exploit parallelism. Consequently, it has been the use of GPUs that made these models work well on real-world problems, and that re-ignited widespread interest in neural networks around 2012. Deep neural networks running on fast parallel hardware currently yield the state-of-the-art, and in some cases better-than-human, performance in tasks that have been considered too hard for computers to solve just a few years ago. These include visual object recognition, action recognition in videos, (fully automated) machine translation, speech recognition, speech synthesis, control.In this tutorial, I will outline some of the core principles behind in Deep Learning, and I will describe the kinds of architectures, learning algorithms, and low-level computations used in commonly deployed models. I will also talk about computational tricks and common software frameworks used in the area, and I will describe current challenges and research directions. [/spoiler]
10:30 AM Break
10:45 AM Deep Learning Common software tools, research questions, outlook  Roland Memisevic University of Montreal

12:15 PM Lunch
1:30 PM Makers from Hobbyists to Professionals Welcome Christopher Nitta UC Davis
[spoiler title=”Abstract:“] In recent years, there has been an explosion of inexpensive, power efficient microcontrollers that year after year have increased in performance while integrating more peripherals. The marker’s community has rapidly adopted these products and integrated them into projects ranging from wearable LED costumes to quadcopter controllers with surveillance. This tutorial will explore the trends of makers from both the hobbyist’s and the professional’s perspective and how these network connected devices fit into the Internet of Things.
Biography: Christopher Nitta is an adjunct professor at UC Davis. Christopher’s current research focus is on computer architecture, but in a “previous life” he dedicated his time to designing and implementing the embedded control systems of plug-in hybrid-electric vehicles, fuel cells, and wind turbines.[/spoiler]
1:40 PM Maker Trends: The Path of Least Resistance Peter Dokter SparkFun
[spoiler title=”Abstract:“] New tech moves fast in the maker community. From RF solutions to sensing applications to microcontrollers, beginners and experts alike are pushing the limits for fun and profit. What are the trends? I’ll cover the most popular parts from SparkFun’s perspective, along with examples of products and projects that we’ve seen in the last few years.
Biography: Pete Dokter is a serial hobbyist now spinning that habit into interesting projects for SparkFun electronics, where he wrangles cats (engineers) as the Director of Engineering. Pete’s also the host of the “According to Pete” video series, where he explains electrical engineering concepts on the internet.[/spoiler]
2:35 PM IoT Device Development Challenges and Solutions Venkat Mattela and Sailaja Dharani Redpine Signals
[spoiler title=”Abstract:“] Internet of Things (IoT) phrase is as prevalent as the word Wi-Fi® today and it is expected to go through the same evolution in awareness for mass market adoption. Wireless communication is the key part of the encompassing components of any IoT device. Wireless connectivity enhances the device utility at the expense of ease of use and deployment challenges. Additionally, realizing the perceived market size of multi-billion devices IoT space requires security solution at all levels at an attractive price point. This presentation provides insights into rapid IoT device development beyond hobbyists.
Biography: Mr. Mattela has over 30 years of engineering and management experience in the semiconductor industry. Prior to joining Redpine, Mr. Mattela was at Network Media Platforms Group of Analog Devices as Director and was responsible for the product, strategy and business development for media wireless connectivity solutions (WLAN, WMAN). Prior to joining ADI, Mr. Mattela was at Infineon Technologies as Director and was responsible for micro-architecture and design of TriCore MCU-DSP processor. Mr. Mattela started his career at Tata Institute of Fundamental Research, India in January 1983 and held various engineering positions at LSI Logic, LMSI and CMC Ltd. Mr. Mattela has a Master’s Degree in Computer Sciences from Jawaharlal Nehru Technological University, India and holds 11 US patents.
Ms. Dharani has started her professional career at Redpine signals and has 13 years of engineering experience in wireless space. At Redpine Signals Ms. Dharani is responsible for system design covering all levels of development including developing silicon integration technologies. She has developed highly optimized embedded platforms using Redpine chipsets. Ms. Dharani received gold medal for her academic excellence in Bachelor’s Degree in Electronics and Communications Engineering from Jawaharlal Nehru Technological University, India and holds 13 US patents. [/spoiler]
3:30 PM Break
3:45 PM Makers (cont) Implementing Software Defined Radio on the Parallella Andreas Olofsson Adapteva
[spoiler title=”Abstract:“] This tutorial will present the Parallella single board computer in detail and show how the board can be used for embedded computing. The Parallella is a $99 credit card sized heterogeneous computing platform that includes a dual core Zynq SOC and a 16 core Epiphany DSP coprocessor. The project was launched on Kickstarter in 2012 and today has over 10,000 developers and 200 Universities. The tutorial will show how to download and run programs on the ARM, how to accelerate key applications using the Zynq FPGA fabric, and how to program the Epiphany manycore DSP. The tutorial will conclude with a complete Software Defined Radio application running on the Parallella.
Biography: Andreas Olofsson founded Adapteva in 2008 with a mission to create a new class of low power parallel processors. Since its inception, Adapteva as a semiconductor company has achieved two “world firsts”: first to build a microprocessor with 50 GFLOPS/Watt processing efficiency and first to successfully crowd fund a chip. Prior to starting Adapteva, Andreas worked at Analog Devices for 10 years developing energy efficiency DSPs and mixed signal SOCs. Andreas holds a BS degree in Physics and BS/MS degrees in Electrical Engineering from the University of Pennsylvania.[/spoiler]
4:40 PM Current trends for hardware & software developers Vrajesh Bhavsar ARM
[spoiler title=”Abstract:“] Wrap up of tutorial with a deeper look into current trends for hardware & software developers. A review of what is enabling the makers and how the “maker principles” are influencing traditional value chains across industries. This presentation will survey changes across application verticals, examining the impact of increasing maker participation and their influence on design and manufacturing processes, as well as on end market product and services opportunities.
Biography: Vrajesh Bhavsar is the Segment Marketing Manager for IoT at ARM, Inc. ARM is a leading semiconductor IP provider, designing scalable, energy-efficient processors and related technologies to deliver the intelligence in applications ranging from sensors to servers, including smartphones, tablets and connected embedded devices. Vrajesh drives strategic ecosystem projects within ARM and is always excited to play with different technologies across the stack.Vrajesh has an extensive engineering background in embedded systems & cloud services. He developed many core technologies at Apple & worked on various R&D projects at Qualcomm. [/spoiler]
5:35 PM Wrap Up

5:45 PM Wine & Cheese Reception
7:00 PM End of Reception
[/tab] [tab title=”Conf. Day1″]

Conference Day 1

Mon 8/24 Session Title Presenter Affiliation
8:15 AM Breakfast
9:15 AM Welcome Introductory Remarks
9:30 AM Internet of Things PULP: A Parallel Ultra-Low-Power Platform for Next Generation IoT Applications 1Davide Rossi, 1Francesco Conti, 1,2Andrea Marongiu, 2Antonio Pullini, 1Igor Loi, 2Michael Gautschi, 1Giuseppe Tagliavini, 2Alessandro Capotondi, 3Philippe Flatresse and 1,2Luca Benini 1DEI, 2ETH, 3ST Micro
Design of an Ultra-low Power SoC Testchip for Wearables & IOT May Wu, Ravishankar Iyer, Yatin Hoskote, Steven Zhang, Bernard Deadman, Mukesh Bhartiya and Yada Satish Intel
Ultra-Low Power Wireless SoCs Enabling a Batteryless IoT Benton Calhoun and David Wentzloff PsiKick

11:00 AM Break
11:30 AM Keynote 1 Convolutional Neural Networks Yann LeCun Facebook

12:30 PM Lunch
1:45 PM Multimedia and Signal Processing Architecture of the V6x Hexagon DSP for Mobile Imaging and Always-On Applications Lucian Codrescu, Eric Mahurin, Mao Zeng, Erich Plondke, Suresh Venkumahanti and Rick Maule Qualcomm
A Scalable Heterogeneous Multicore Architecture for ADAS Zoran Nikolic, Rama Venkatasubramanian, Jason Jones and Peter Labaziewicz TI
Energy Efficient Graphics and Multi-media in 28nm Carrizo APU Guhan Krishnan, Dan Bouvier, Praveen Dongara and Louis Zhang AMD
Revisiting DSP Acceleration with the Kalray MPPA Manycore Processor Benoît Dupont de Dinechin Kalray

3:45 PM Break
4:15 PM High Performance, Cloud Computing and Communication Mars: A 64-Core ARMv8 Processor Charles Zhang Phytium
LS2085A Freescale’s new QorIQ Layerscape Communications Processor John Xu and Sam Fuller Freescale
Oracle’s Sonoma Processor: Advanced low-cost SPARC processor for enterprise workloads Basant Vinaik and Rahoul Puri Oracle
I/O Virtualization and System Acceleration in Power8 Michael Gschwind IBM

6:15 PM Reception
7:15 PM End of Reception
[/tab] [tab title=”Conf. Day2″]

Conference Day 2

Tue 8/25 Session Title Presenter Affiliation
7:30 AM Breakfast
8:30 AM FPGAs Xilinx 16nm UltraScale+ MPSoC and FPGA Families Vamsi Boppana, Sagheer Ahmad, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan and Ralph Wittig Xilinx
Stratix 10 Altera’s 14nm FPGA Targeting 1GHz Performance Mike Hutton Altera
Toward Accelerating Deep Learning at Scale Using Specialized Logic Kalin Ovtcharov, Olatunji Ruwase, Joo-Young Kim, Jeremy Fowers, Karin Strauss and Eric Chung Microsoft Research

10:00 AM Break
10:30 AM GPUs MIAOW – An Open Source GPGPU Raghu Balasubramanian, Vinay Gangadhar, Ziliang Guo, Chen-Han Ho, Cherin Joseph, Jai Menon, Mario Drumond, Robin Paul, Pradip Valathol and Karu Sankaralingam University of Wisconsin
AMD’s next Generation GPU and Memory Architecture Joe Macri, Raja Koduri, Mike Mantor and Bryan Black AMD
The ARM Mali-T880 Mobile GPU Ian Bratt ARM

12:00 PM Lunch
1:15 PM Keynote 2 The Road to 5G Matt Grob CTO, Qualcomm

2:15 PM Break
2:45 PM Applications Professional H.265/HEVC Encoder LSI Toward High-Quality 4K/8K Broadcast Infrastructure Hiroe Iwasaki, Takayuki Onishi, Ken Nakamura, Koyo Nitta, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Mitsuo Ikeda and Atsushi Simizu NTT
Ultra-low-light CMOS Biosensor Helps Tackle Infectious Diseases Zhimin Ding Anitoa
Five-Speed PHY Enables 2.5Gbps and 5Gbps Ethernet Rates Over Legacy Copper Cables Ramin Shirani & Ramin Farjadrad Aquantia

4:15 PM Break
4:45 PM Processors Knights Landing: 2nd Generation Intel “Xeon Phi” Processor Avinash Sodani Intel
Intel “Xeon” Processor D: The first Xeon processor optimized for dense solutions Dheemanth Nagaraj and Chris Gianos Intel
Raven: A 28nm RISC-V Vector Processor with Integrated Switched-Capacitor DC-DC Converters and Adaptive Clocking Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian Richards, Elad Alon, Borivoje Nikolic and Krste Asanovic University of Berkeley
Intel Atom-X5/X7-8000 Series Processors, Codenamed Cherry Trail Steven Tu Intel

6:45 PM Closing Remarks
[/tab] [tab title=”Posters”]

Posters (** = Awarded Best Poster of Conference)

Title Presenter
Anti-Virus in Silicon ** Adrian Tang, John Demme, Simha Sethumadhavan and Salvatore Stolfo of Columbia University
Lagopus FPGA – a reprogrammable data plane for high-performance software SDN switches. Koji Yamazaki, Yoshihiro Nakajima, Takahiro Hatano and Akihiko Miyazaki of NTT Labs
Why Microarchitecture Matters for Successful Security Library Implementations Sami Saab, Pankaj Rohatgi, Craig Hampel, Jeremy Cooper and Elke De Mulder of Cryptography Research
Comparison of Key/Value Store (KVS) in Software and Programmable Hardware John Lockwood of Algo-Logic
NMI: A New Memory Interface for Cellphones to Supercomputers David Roberts, Amin Farmahini-Farahani, Kevin Cheng, Nathan Hu and Michael Ignatowski of AMD Research
Flexible Video Processing Platform for 8K UHD TV Sukjin Kim, Young-Hwan Park, Jaehyun Kim, Minsoo Kim, Wonchang Lee and Shihwa Lee of Samsung
A Low-power and Real-time Augmented Reality Processor for the Next Generation Smart Glasses Gyeonghoon Kim and Hoi-Jun Yoo of Korea Advanced Institute of Science and Technology
Under 100-cycle Thread Migration Latency in a Single-ISA Heterogeneous Multi-core Processor Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Steve Lipa, Brandon Dwiel, Eric Rotenberg, W. Rhett Davis and Paul D. Franzon of North Carolina State University
[/tab] [/tabs] [/accordion]